Renesas Electronics FIFO Memory, 28-Pin PDIP, 7202LA12TPG
- RS Stock No.:
- 262-8981P
- Mfr. Part No.:
- 7202LA12TPG
- Manufacturer:
- Renesas Electronics
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Currently unavailable
We don't know if this item will be back in stock, RS intend to remove it from our range soon.
- RS Stock No.:
- 262-8981P
- Mfr. Part No.:
- 7202LA12TPG
- Manufacturer:
- Renesas Electronics
Specifications
Product overview and Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | FIFO Memory | |
| Organisation | 1024 x 9 bit | |
| Data Bus Width | 9bit | |
| Access Time | 12ns | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 4.5V | |
| Package Type | PDIP | |
| Pin Count | 28 | |
| Maximum Supply Voltage | 5.5V | |
| Bus Direction | Bi-Directional | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Length | 34.3mm | |
| Height | 2.79mm | |
| Series | IDT7202LA | |
| Width | 7.62mm | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Supply Current | 80mA | |
| Number of Bits per Word | 9 | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type FIFO Memory | ||
Organisation 1024 x 9 bit | ||
Data Bus Width 9bit | ||
Access Time 12ns | ||
Mount Type Surface | ||
Minimum Supply Voltage 4.5V | ||
Package Type PDIP | ||
Pin Count 28 | ||
Maximum Supply Voltage 5.5V | ||
Bus Direction Bi-Directional | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Length 34.3mm | ||
Height 2.79mm | ||
Series IDT7202LA | ||
Width 7.62mm | ||
Standards/Approvals No | ||
Automotive Standard No | ||
Supply Current 80mA | ||
Number of Bits per Word 9 | ||
- COO (Country of Origin):
- TH
The Renesas Electronics FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a retransmit capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.
Pin and functionally compatible with 720X family
Low power consumption
Ultra high speed 12ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
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