Winbond SDRAM 1 GB Surface, 60-Pin 16 bit VFBGA
- RS Stock No.:
- 242-0778
- Mfr. Part No.:
- W971GG8NB25I
- Manufacturer:
- Winbond
The image is for reference only, please refer to product details and specifications
Bulk discount available
View bulk pricing optionsSubtotal (1 tray of 264 units)*
HK$11,167.992
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Units | Per unit | Per Tray* |
|---|---|---|
| 264 - 1056 | HK$42.303 | HK$11,167.99 |
| 1320 + | HK$41.457 | HK$10,944.65 |
*price indicative
- RS Stock No.:
- 242-0778
- Mfr. Part No.:
- W971GG8NB25I
- Manufacturer:
- Winbond
Specifications
Product overview and Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Winbond | |
| Product Type | SDRAM | |
| Memory Size | 1GB | |
| Data Bus Width | 16bit | |
| Number of Bits per Word | 8 | |
| Maximum Random Access Time | 0.4ns | |
| Number of Words | 128M | |
| Mount Type | Surface | |
| Package Type | VFBGA | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 60 | |
| Maximum Operating Temperature | 95°C | |
| Series | W971GG8NB | |
| Length | 9.1mm | |
| Height | 0.65mm | |
| Standards/Approvals | RoHS | |
| Minimum Supply Voltage | 1.7V | |
| Maximum Supply Voltage | 1.9V | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Winbond | ||
Product Type SDRAM | ||
Memory Size 1GB | ||
Data Bus Width 16bit | ||
Number of Bits per Word 8 | ||
Maximum Random Access Time 0.4ns | ||
Number of Words 128M | ||
Mount Type Surface | ||
Package Type VFBGA | ||
Minimum Operating Temperature -40°C | ||
Pin Count 60 | ||
Maximum Operating Temperature 95°C | ||
Series W971GG8NB | ||
Length 9.1mm | ||
Height 0.65mm | ||
Standards/Approvals RoHS | ||
Minimum Supply Voltage 1.7V | ||
Maximum Supply Voltage 1.9V | ||
Automotive Standard No | ||
The Winbond SDRAM is a 1G bits DDR2 SDRAM which is organized as 16,777,216 words, 8 banks, 8 bits. This device achieves high speed transfer rates for various applications.
Two data transfers per clock cycle
Edge-aligned with read data and centre-aligned with write data
DLL aligns DQ and DQS transitions with clock
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