ISSI IS42S32400J-6BLI SDRAM 128 MB Surface Mount, 90-Pin 32 bit BGA
- RS Stock No.:
- 648-081
- Mfr. Part No.:
- IS42S32400J-6BLI
- Manufacturer:
- ISSI
N
Subtotal (1 unit)*
HK$35.82
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- Shipping from 12 February 2027
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Units | Per unit |
|---|---|
| 1 + | HK$35.82 |
*price indicative
- RS Stock No.:
- 648-081
- Mfr. Part No.:
- IS42S32400J-6BLI
- Manufacturer:
- ISSI
Specifications
Product overview and Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | ISSI | |
| Product Type | SDRAM | |
| Memory Size | 128MB | |
| Organisation | 1M bit | |
| Data Bus Width | 32bit | |
| Address Bus Width | 12bit | |
| Maximum Clock Frequency | 166MHz | |
| Maximum Random Access Time | 6ns | |
| Mount Type | Surface Mount | |
| Package Type | BGA | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 90 | |
| Maximum Operating Temperature | 85°C | |
| Series | IS42S32400J | |
| Standards/Approvals | RoHS | |
| Automotive Standard | No | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 3.6V | |
| Supply Current | 120mA | |
| Select all | ||
|---|---|---|
Brand ISSI | ||
Product Type SDRAM | ||
Memory Size 128MB | ||
Organisation 1M bit | ||
Data Bus Width 32bit | ||
Address Bus Width 12bit | ||
Maximum Clock Frequency 166MHz | ||
Maximum Random Access Time 6ns | ||
Mount Type Surface Mount | ||
Package Type BGA | ||
Minimum Operating Temperature -40°C | ||
Pin Count 90 | ||
Maximum Operating Temperature 85°C | ||
Series IS42S32400J | ||
Standards/Approvals RoHS | ||
Automotive Standard No | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 3.6V | ||
Supply Current 120mA | ||
The ISSI 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V VDD and 3.3V VDDQ memory systems containing 134,217,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows by 256 columns by 32 bits. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 128Mb SDRAM has the Ability to synchronously burst data at a high data rate with automatic column-address generation, the Ability to interleave between internal banks to hide recharge time and the capAbility to randomly change column addresses on each clock cycle during burst access.
Auto Refresh (CBR)
Self Refresh
LVTTL Interface
Random column address every clock cycle
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