Intelligent Memory IM2G04D2DBBG-25 SDRAM 2 GB Surface, 60-Pin 16 bit FBGA-60 Ball
- RS Stock No.:
- 588-600
- Mfr. Part No.:
- IM2G04D2DBBG-25
- Manufacturer:
- Intelligent Memory
Subtotal (1 unit)*
HK$206.40
FREE delivery for orders over HK$250.00
In Stock
- 50 unit(s) ready to ship from another location
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit |
|---|---|
| 1 + | HK$206.40 |
*price indicative
- RS Stock No.:
- 588-600
- Mfr. Part No.:
- IM2G04D2DBBG-25
- Manufacturer:
- Intelligent Memory
Specifications
Product overview and Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Intelligent Memory | |
| Memory Size | 2GB | |
| Product Type | SDRAM | |
| Data Bus Width | 16bit | |
| Maximum Clock Frequency | 533MHz | |
| Maximum Random Access Time | 2.5ns | |
| Mount Type | Surface | |
| Package Type | FBGA-60 Ball | |
| Pin Count | 60 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 95°C | |
| Series | IM2G | |
| Standards/Approvals | JEDEC, RoHS | |
| Automotive Standard | AEC-Q100 | |
| Maximum Supply Voltage | 1.9V | |
| Minimum Supply Voltage | 1.7V | |
| Select all | ||
|---|---|---|
Brand Intelligent Memory | ||
Memory Size 2GB | ||
Product Type SDRAM | ||
Data Bus Width 16bit | ||
Maximum Clock Frequency 533MHz | ||
Maximum Random Access Time 2.5ns | ||
Mount Type Surface | ||
Package Type FBGA-60 Ball | ||
Pin Count 60 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 95°C | ||
Series IM2G | ||
Standards/Approvals JEDEC, RoHS | ||
Automotive Standard AEC-Q100 | ||
Maximum Supply Voltage 1.9V | ||
Minimum Supply Voltage 1.7V | ||
The Intelligent Memory DDR DRAM achieves high-speed data transfer rates by employing a chip architecture that prefetches multiple bits and synchronizes the output data to a system clock. It supports system frequencies up to 533 MHz, enabling fast and efficient performance. The design includes internal banks for concurrent operation and utilizes a 4-bit prefetch architecture to boost data throughput.
RoHS compliant
PASR partial array self refresh
Auto refresh and self refresh
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