Alliance Memory AS4C1G16D4-062BCN SDRAM 16 GB Surface, 96-Pin 16 bit FBGA-96 Ball
- RS Stock No.:
- 425-204
- Mfr. Part No.:
- AS4C1G16D4-062BCN
- Manufacturer:
- Alliance Memory
Subtotal (1 tray of 190 units)*
HK$225,141.83
Stock information currently inaccessible - Please check back later
Units | Per unit | Per Tray* |
|---|---|---|
| 190 + | HK$1,184.957 | HK$225,141.83 |
*price indicative
- RS Stock No.:
- 425-204
- Mfr. Part No.:
- AS4C1G16D4-062BCN
- Manufacturer:
- Alliance Memory
Specifications
Product overview and Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Alliance Memory | |
| Memory Size | 16GB | |
| Product Type | SDRAM | |
| Data Bus Width | 16bit | |
| Maximum Clock Frequency | 1600MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 13.75ns | |
| Mount Type | Surface | |
| Package Type | FBGA-96 Ball | |
| Minimum Operating Temperature | 0°C | |
| Pin Count | 96 | |
| Maximum Operating Temperature | 95°C | |
| Height | 13mm | |
| Standards/Approvals | JEDEC JESD-79-4 | |
| Series | AS4C1G16D4 | |
| Length | 16mm | |
| Automotive Standard | No | |
| Minimum Supply Voltage | 1.14V | |
| Maximum Supply Voltage | 1.2V | |
| Select all | ||
|---|---|---|
Brand Alliance Memory | ||
Memory Size 16GB | ||
Product Type SDRAM | ||
Data Bus Width 16bit | ||
Maximum Clock Frequency 1600MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 13.75ns | ||
Mount Type Surface | ||
Package Type FBGA-96 Ball | ||
Minimum Operating Temperature 0°C | ||
Pin Count 96 | ||
Maximum Operating Temperature 95°C | ||
Height 13mm | ||
Standards/Approvals JEDEC JESD-79-4 | ||
Series AS4C1G16D4 | ||
Length 16mm | ||
Automotive Standard No | ||
Minimum Supply Voltage 1.14V | ||
Maximum Supply Voltage 1.2V | ||
- COO (Country of Origin):
- CN
The Alliance Memory DDR4 SDRAM is a high-speed dynamic random-access memory internally organized with eight-banks. DDR4 SDRAM uses a 8n prefect architecture to achieve high-speed operation. Operation begins with the registration of an Activate Command, which is then followed by a Read or Write command.
ZQ Calibration
JEDEC Standard Compliant
Write Leveling
RoHS compliant
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