Nexperia 74HCT373D,653 Octal D Type Latch, 8-Bit Non-Inverting, 20-Pin SO
- RS Stock No.:
- 170-4869
- Mfr. Part No.:
- 74HCT373D,653
- Manufacturer:
- Nexperia
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HK$4,046.00
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Units | Per unit | Per Reel* |
|---|---|---|
| 2000 - 2000 | HK$2.023 | HK$4,046.00 |
| 4000 + | HK$1.942 | HK$3,884.00 |
*price indicative
- RS Stock No.:
- 170-4869
- Mfr. Part No.:
- 74HCT373D,653
- Manufacturer:
- Nexperia
Specifications
Product overview and Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Logic Family | 74HCT | |
| Product Type | Octal D Type Latch | |
| Logic Function | D Type | |
| Number of Channels | 8 | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Package Type | SO | |
| Pin Count | 20 | |
| Minimum Supply Voltage | 4.5V | |
| Input Level | TTL | |
| Maximum Supply Voltage | 5.5V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Propagation Delay Time @ CL | 45ns | |
| Maximum Operating Temperature | 125°C | |
| Length | 13mm | |
| Standards/Approvals | No | |
| Series | 74HCT | |
| Height | 2.45mm | |
| Output Type | 3 State | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Logic Family 74HCT | ||
Product Type Octal D Type Latch | ||
Logic Function D Type | ||
Number of Channels 8 | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Package Type SO | ||
Pin Count 20 | ||
Minimum Supply Voltage 4.5V | ||
Input Level TTL | ||
Maximum Supply Voltage 5.5V | ||
Minimum Operating Temperature -40°C | ||
Maximum Propagation Delay Time @ CL 45ns | ||
Maximum Operating Temperature 125°C | ||
Length 13mm | ||
Standards/Approvals No | ||
Series 74HCT | ||
Height 2.45mm | ||
Output Type 3 State | ||
Automotive Standard No | ||
- COO (Country of Origin):
- CN
The 74HC373, 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE.
Mixed 5 V and 3.3 V applications
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
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