Nexperia 74LVC273PW,118 D Type Flip Flop IC, D Type Flip-Flop, 20-Pin TSSOP
- RS Stock No.:
- 170-5348
- Mfr. Part No.:
- 74LVC273PW,118
- Manufacturer:
- Nexperia
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Added
Price Each (In a Pack of 25)
HK$3.61
| Units | Per unit | Per Pack* |
| 25 - 600 | HK$3.61 | HK$90.25 |
| 625 - 1225 | HK$3.52 | HK$88.00 |
| 1250 + | HK$3.466 | HK$86.65 |
| *price indicative | ||
- RS Stock No.:
- 170-5348
- Mfr. Part No.:
- 74LVC273PW,118
- Manufacturer:
- Nexperia
Product overview and Technical data sheets
Legislation and Compliance
- COO (Country of Origin):
- CN
Product Details
The 74LVC273 has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
For products that are Customized and under Non-cancellable & Non-returnable, Sales & Conditions apply.
Specifications
Attribute | Value |
|---|---|
| Logic Family | 74LVC |
| Logic Function | D Type |
| Input Type | Single Ended |
| Output Type | D Type Flip-Flop |
| Output Signal Type | Single Ended |
| Triggering Type | Positive Edge |
| Polarity | Non-Inverting |
| Mounting Type | Surface Mount |
| Package Type | TSSOP |
| Pin Count | 20 |
| Set/Reset | Master Reset |
| Number of Elements per Chip | 1 |
| Maximum Propagation Delay Time @ Maximum CL | 22.2 ns @ 50 pF |
| Maximum Operating Supply Voltage | 3.6 V |
| Dimensions | 6.6 x 4.5 x 0.95mm |
| Propagation Delay Test Condition | 50pF |
| Maximum Operating Temperature | +125 °C |
| Length | 6.6mm |
| Height | 0.95mm |
| Width | 4.5mm |
| Minimum Operating Temperature | -40 °C |
| Minimum Operating Supply Voltage | 1.65 V |